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| December 1997 S IG N DES NEW at FO R nter D NDE I5810 port Ce /tsc E OMM See H icl Sup rsil.com REC te hn T e c w w w .in NOT o ur r o ct S IL ont a or c 8-INTER 1-88 (R) HI-7153 8-Channel, 10-Bit High Speed Sampling A/D Converter Features * 5s Conversion Time * 8 Channel Input Multiplexer * 200,000 Channels/Second Throughput Rate * Over 9 Effective Bits at 20kHz * No Offset or Gain Adjustments Necessary * Analog and Reference Inputs Fully Buffered * On-Chip Track and Hold Amplifier * P Compatible Interface * 2's Complement Data Output * 150mW Power Consumption * Only a Single 2.5V Reference Required for a 2.5V Input Range * Out-of-Range Flag * /883 Version Available Description The HI-7153 is an 8 channel high speed 10 bit A/D converter which uses a Two Step Flash algorithm to achieve through-put rates of 200kHz. The converter features an 8 channel CMOS analog multiplexer with random channel addressing. A unique switched capacitor technique allows a new input voltage to be sampled while a conversion is taking place. Internal high speed CMOS buffers at both the analog and reference inputs simplifies interface requirements. A Track and Hold amplifier is included on the chip, consisting of two high speed amplifiers and an internal hold capacitor, reducing external circuitry. Microprocessor bus interfacing is simplified by the use of standard Chip Select, Read, and Write control signals. The digital three-state outputs are byte organized for bus interface to 8 or 16 bit systems. An Out-of-Range pin, together with the MSB bit, can be used to indicate an under or over-range condition. The HI-7153 operates with 5V supplies. Only a single +2.5V reference is required to provide a bipolar input range from -2.5V to +2.5V. Applications * P Controlled Data Acquisition Systems * DSP - Avionics - Sonar * Process Control - Automotive Transducer Sensing - Industrial * Robotics * Digital Communications Ordering Information PART NUMBER HI3-7153J-5 HI3-7153A-9 HI1-7153S-2 LINEARITY (MAX ILE) TEMPERATURE RANGE 0oC to +70oC -40oC to +85oC PACKAGE 40 Lead Plastic DIP 40 Lead Plastic DIP 1.0 LSB 1.0 LSB 1.0 LSB -55oC to +125oC 40 Lead Ceramic DIP DO Functional Diagram VREF RESISTOR LADDER REF AMP REF INVERT + - 33 TWO STEP FLASH LATCHES AND OUTPUT BUFFERS DATA OUTPUTS D9 OVR BUS HBE (ANALOG GND) AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 A0 A1 A2 ALE TEST (DIGITAL GND) AG INPUT BUFFER AMP 1 BUS CTRL HOLD MUX TRACK HOLD AMP CONTROL LOGIC V+ VGND DG POWER SUPPLY DISTRIBUTION RD WR CS SMODE CLK EOC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1 File Number 2787.4 HI-7153 Pinouts HI-7153 (CDIP, PDIP) TOP VIEW VREF AG AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 1 2 3 4 5 6 7 8 9 10 40 V39 GND 38 V+ 37 OVR 36 D9 (MSB) 35 D8 34 D7 33 D6 32 D5 31 D4 30 D3 29 D2 28 D1 27 D0 (LSB) 26 HOLD 25 EOC 24 DG 23 CLK 22 HBE 21 BUS NC 11 TEST 12 A0 13 A1 14 A2 15 ALE 16 WR 17 CS 18 RD 19 SMODE 20 2 HI-7153 Absolute Maximum Ratings Supply Voltage V+ to GND (DG/AG/GND) . . . . . . . . . . . . . . . -0.3V < V+ < +5.7V V- to GND (DG/AG/GND) . . . . . . . . . . . . . . . . .-5.7V < V- < +0.3V Analog InputPins (Note 1) (A IN0 - AIN7, VREF) . . . . . . . . . . . . . . . V- -0.3V < VINA < V+ +0.3V Digital I/O Pins (Note 1) . . . . . . . . . . . . . DG -0.3V Thermal Information Thermal Resistance JA Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50oC/W Operating Temperature Range HI3-7153X-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC HI3-7153X-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC HI1-7153X-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Derate above +70oC at 10mW/oC Electrical Specifications V+ = +5V, V- = -5V, VREF = +2.50V, fCLK = 600kHz, t R = t F 25ns, 50% Duty Cycle. All Typical Values have been Characterized but are Not Tested. (NOTE 3) J, A, S GRADE SYMBOL TEMPERATURE MIN TYP MAX UNITS (NOTE 4) PARAMETER ACCURACY Resolution (Note 5) RES TA = +25oC TMIN TA TMAX TA = +25oC TMIN TA TMAX TA = +25oC TMIN TA TMAX TA = +25oC TMIN TA TMAX TA = +25oC TMIN TA TMAX TA = +25oC TMIN TA TMAX 10 10 - 0.5 0.75 0.5 0.75 1.0 1.5 1.0 1.5 0.002 0.002 1.0 1.0 1.0 1.0 2.5 3.0 2.5 3.0 - Bits Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB Integral Linearity Error ILE Differential Linearity Error DLE Bipolar Offset Error VOS Unadjusted Gain Error FSE Channel to Channel Mismatch NOTES: 1. Input voltages may exceed the supply voltage, one input or channel at a time, provided the input current is limited to 10mA. 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. See Ordering Information Table. 4. FSR (Full Scale Range) = 2 x VREF (5.00V at VREF = 2.50V). LSB (Least Significant Bit) = FSR/1024 (4.88mV at VREF = 2.50V). 5. Parameter Not tested. Parameter guaranteed by design, simulation, or characterization. 6. TMIN and TMAX limits guaranteed by +25oC test. 3 HI-7153 Electrical Specifications o TA = +25 C, V+ = +5V, V- = -5V, VREF = +2.50V, fCLK = 600kHz, tR = tF 25ns, 50% Duty Cycle. All Typical Values have been Characterized but are Not Tested. +25oC SYMBOL CONDITIONS TYP UNITS (NOTE 1) PARAMETER DYNAMIC CHARACTERISTICS Signal to Noise Ratio SNR fIN = 4.932kHz, 2.5V fIN = 14.697kHz, 2.5V fIN = 24.462kHz, 2.5V fIN = 43.994kHz, 2.5V 59 59 58 56 59 58 55 48 -66 -61 -56 -48 -76 -77 -77 -74 dB dB dB dB dB dB dB dB dBc dBc dBc dBc dB dB dB dB Signal to Noise + Distortion SINAD fIN = 4.932kHz, 2.5V fIN = 14.697kHz, 2.5V fIN = 24.462kHz, 2.5V fIN = 43.994kHz, 2.5V Total Harmonic Distortion THD fIN = 4.932kHz, 2.5V fIN = 14.697kHz, 2.5V fIN = 24.462kHz, 2.5V fIN = 43.994kHz, 2.5V Spurious-Free Dynamic Range SFDR fIN = 4.932kHz, 2.5V fIN = 14.697kHz, 2.5V fIN = 24.462kHz, 2.5V fIN = 43.994kHz, 2.5V NOTE: 1. FSR (Full Scale Range) = 2 x VREF (5.00V at VREF = 2.50V). LSB (Least Significant Bit) = FSR/1024 (4.88mV at VREF = 2.50V) DC Electrical Specifications TA = +25oC, V+ = +5V, V- = -5V, VREF = +2.50V, fCLK = 600kHz, t R = tF 25ns, 50% Duty Cycle, Unless Otherwise Specified. All Typical Values have been Characterized but are Not Tested. +25oC 0 oC MAX MIN to +75oC MAX -40oC to +85oC MIN MAX -55oC to +125o C MIN MAX UNIT (NOTE 1) PARAMETER SYMBOL CONDITIONS MIN TYP ANALOG MULTIPLEXER INPUT Input Range Input Resistance Input Leakage Current On Channel Input Capacitance Off Channel Input Capacitance MUX On-Resistance Greatest Change in RDS(ON) Between Any Two Channels VIR RIN IBI CA IN(ON) CAIN(OFF) RDS(ON) RDS(ON) AIN = 0V AIN = 0V, Note 2 AIN = 0V, Note 2 AIN = 2.5V, IIN =100A -2.5V AIN +2.5V -VREF 10 0.01 10 8 1.1 2.5 +VREF 100 30 20 2.5 -VREF +VREF 100 30 20 2.5 -VREF +VREF 100 30 20 2.5 -VREF +VREF 100 30 20 2.5 V M nA pF pF K % 4 HI-7153 DC Electrical Specifications TA = +25oC, V+ = +5V, V- = -5V, VREF = +2.50V, fCLK = 600kHz, t R = tF 25ns, 50% Duty Cycle, Unless Otherwise Specified. All Typical Values have been Characterized but are Not Tested. +25oC SYMBOL OIRR CCRR CONDITIONS FIN =100kHz, Note 4 FIN =100kHz, Note 4 MIN TYP -96 -83 MAX 0oC to +75oC MIN MAX -40oC to +85oC MIN MAX -55oC to +125o C MIN MAX UNIT dB dB (Con- (NOTE 1) PARAMETER Off-Channel Isolation Channel to Channel Isolation REFERENCE INPUT Reference Input Range Reference Input Bias Current Reference Input Capacitance LOGIC INPUTS Input High Voltage Input Low Voltage Logic Input Current Input Capacitance LOGIC OUTPUTS Output High Voltage Output Low Voltage Output Leakage Current VOH VOL IOL IOH = -200A IOL = 1.6mA RD = +5V, VOUT = +5V RD = +5V, VOUT = 0V Output Capacitance COUT High-Z State, Note 2 2.4 -1 0.04 -0.01 7 0.4 1 15 2.4 -10 0.4 10 2.4 -10 0.4 10 2.4 -10 0.4 10 V V A A pF V IH VIL IIL CIN VIN = 0V, +5V Note 2 2.4 0.05 7 0.8 1 17 2.4 0.8 1 2.4 0.8 1 2.4 0.8 1 V V A pF VRR IBR CVR Note 3 VREF = +2.50V Note 2 2.2 0.01 8 2.6 100 20 2.2 2.6 100 2.2 2.6 100 2.2 2.6 100 V nA pF POWER SUPPLY VOLTAGE RANGE V+ VPOWER SUPPLY REJECTION V+, V- Gain Error FSE V+ = 5V, V- = -4.75V, -5.25V V- = -5V, V+ = 4.75V, 5.25V V+, V- Offset Error VOS V+ = 5V, V- = -4.75V, -5.25V V- = -5V, V+ = 4.75V, 5.25V 0.1 0.5 0.6 0.6 0.8 LSB Functional Operation Only, Note 3 4.5 -4.5 5.0 -5.0 5.5 -5.5 4.5 -4.5 5.5 -5.5 4.5 -4.5 5.5 -5.5 4.5 -4.5 5.5 -5.5 V V - 0.1 0.5 - 0.6 - 0.6 - 0.8 LSB - 0.15 0.5 - 0.6 - 0.6 - 0.8 LSB - 0.15 0.5 - 0.6 - 0.6 - 0.8 LSB 5 HI-7153 DC Electrical Specifications TA = +25oC, V+ = +5V, V- = -5V, VREF = +2.50V, fCLK = 600kHz, t R = tF 25ns, 50% Duty Cycle, Unless Otherwise Specified. All Typical Values have been Characterized but are Not Tested. +25oC SYMBOL CONDITIONS MIN TYP MAX 0oC to +75oC MIN MAX -40oC to +85oC MIN MAX -55oC to +125o C MIN MAX UNIT (Con- (NOTE 1) PARAMETER SUPPLY CURRENTS V+ Supply Current V- Supply Current GND Current DG Current AG Current NOTES: 1. FSR (Full Scale Range) = 2 x VREF (5.00V at VREF = 2.50V). LSB (Least Significant Bit) = FSR/1024 (4.88mV at VREF = 2.50V) 2. Parameter Not tested. Parameter guaranteed by design, simulation, or characterization 3. Functionality is guaranteed by negative GAIN ERROR test. 4. Channel Isolation is tested with an input signal of 2.5Vp-p, 100kHz and the measured pin is loaded with 100 to GND I+ IIGND IDG IAG V+ = 5V, V- = -5V, VIN = 0V, Digital Outputs Are Unloaded 20 -10 -8 -2 0.02 30 -15 30 -15 30 -15 30 -15 mA mA mA mA A DC Electrical Specifications TA = +25oC, V+ = 5V 10%, V- = -5V, VREF = 2.50V, fCLK = 600kHz, tR = t F 25ns, 50% Duty Cycle, CL = 100pF (Including Stray for D0-D9, OVR, HOLD), Unless Otherwise Specified. All Typical Values have been Characterized but are Not Tested. +25 C o (NOTE 4) PARAMETER 0 C to +75 C MAX MIN MAX o o -40 C to +85 C MIN MAX o o -55oC to +125oC MIN MAX UNIT SYMBOL CONDITIONS MIN TYP TIMING CHARACTERISTICS Continuous Conversion Time tSPS Note 2 Note 9 Notes 2, 8 Conversion Time, First Conversion Continuous Throughput Clock Period Clock Input Duty Cycle ALE Pulse Width Address Setup Time Address Hold Time WR Pulse Width WR to EOC Low WR to HOLD Delay Clock to HOLD Rise Delay Clock to HOLD Fall Delay tCONV tCYC tCLK D tALEW tAS tAH tWRL tWREOC tHOLD tCKHR tCKHF Notes 1, 3, 9 Notes 1, 9 Notes 1, 9 Note 9 Notes 2, 9 Note 9 Note 9 Note 9 Notes 1, 9 Note 2 60 45 30 40 0 100 150 50 1/fCLK 50 15 15 -16 20 80 80 265 95 5 3tCLK 4tCLK + 0.63 tCLK/3 55 tCLK/2 130 150 450 200 60 45 40 80 0 100 140 40 5 3tCLK 4tCLK + 0.75 tCLK/3 55 tCLK/2 160 170 500 225 60 45 40 80 0 100 120 40 5 3tCLK 4tCLK + 0.75 tCLK/3 55 tCLK/2 160 170 500 225 60 45 50 80 0 100 120 40 5 3tCLK 4tCLK + 0.8 tCLK/3 55 tCLK/2 160 170 500 225 s s s s CPS % ns ns ns ns ns ns ns ns 6 HI-7153 DC Electrical Specifications TA = +25oC, V+ = 5V 10%, V- = -5V, VREF = 2.50V, fCLK = 600kHz, tR = t F 25ns, 50% Duty Cycle, CL = 100pF (Including Stray for D0-D9, OVR, HOLD), Unless Otherwise Specified. All Typical Values have been Characterized but are Not Tested. +25oC SYMBOL tCKEOC tDATA tCD tAD tRD tRX tR tF CONDITIONS Notes 1, 9 Notes 2, 9 Note 9 Note 9 Notes 6, 9 Notes 7, 9 Notes 5, 9 Notes 5, 9 MIN 100 TYP 460 200 40 30 70 30 20 15 MAX 630 350 70 50 100 60 40 30 0oC to +75oC MIN 90 MAX 750 400 85 70 125 70 60 50 (Continued) (NOTE 4) PARAMETER Clock to EOC High HOLD to DATA Change CS to DATA HBE to DATA RD LOW to Active RD HIGH to Inactive Output Rise Time Output Fall Time NOTES: -40o C to +85oC MIN 90 MAX 750 400 85 70 125 70 60 50 -55oC to +125oC MIN 90 MAX 800 400 85 70 125 70 60 50 UNIT ns ns ns ns ns ns ns ns 1. Slow memory mode timing 2. Fast memory or DMA mode of operation, except the first conversion which is equal to tCONV 3. Maximum specification to prevent multiple triggering with WR 4. All input drive signals are specified with tR = tF 10ns and shall swing from 0.4V to 2.4V for all timing specifications. A signal is considered to change state as it crosses a 1.4V threshold (except tRD and tRX) 5. tR and tF load is CL = 100pF (including stray capacitance) to DG and is measured from the 10% - 90% point 6. tRD is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. High-Z to VOH is measured with R L = 2.5K and CL = 100pF (including stray) to DG. High-Z to VOL is measured with R L = 2.5K to V+ and CL = 100pF (including stray) to DG 7. tRX is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. VOH to High-Z is measured with RL = 2.5K and CL = 10pF (including stray) to DG. VOL to High-Z is measured with RL = 2.5K to V+ and CL = 10pF (including stray) to DG 8. For clock frequencies other than 600kHz 9. Parameter Not Tested. Parameter guaranteed by design, simulation, or characterization 7 HI-7153 Timing Diagrams FAST MEMORY MODE (8 BIT DATA BUS) 0 CLOCK tCD tSPS tCKHF TRACK N+1 HOLD N+1 tCKHR TRACK N+2 HOLD N+2 TRACK N+3 tALEW ALE tAH tAS A0 - A2 INTERNAL DATA N-1 DATA tDATA N DATA N+3 ADDRESS N+1 DATA 1 2 3 CS (WR MAY BE WIRED LOW) tHOLD HOLD N WR HOLD TRACK N RD tRD tAD tRX D0 - D9, OVR DATA HIGH BYTE N DATA LOW BYTE HIGH BYTE N+1 DATA LOW BYTE HBE CONDITIONS: SMODE = DG. Bus = DG NOTE: With SMODE = DG, the internal logic diables the output latches from being updated during a read. The EOC output is LOW continuously. DMA MODE (16 BIT DATA BUS) CLOCK ALE A0 - A2 N+1 ADDRESS N+2 ADDRESS N+3 ADDRESS HOLD TRACK N HOLD N TRACK N+1 HOLD N+1 TRACK N+2 HOLD N+2 INTERNAL DATA N-1 DATA N DATA N+1 DATA D0 - D9, OVR DATA N-1 DATA N DATA N+1 DATA CONDITIONS: SMODE = V+, CS = WR = RD = DG, Bus = V+, HBE = DG or V+ NOTE: EOC output is low continuously 8 HI-7153 Timing Diagrams (Continued) SLOW MEMORY MODE (16 BIT DATA BUS) 0 CLOCK 1 2 3 tCK CS tWR WR tSLEW ALE tAS tAH AO - A2 N ADDRESS tHOLD HOLD TRACK N HOLD N tCKHR TRACK N+1 INTERNAL DATA N-1 DATA N DATA RD tWREOC tCKEOC EOC tRD D0 - D9, OVR DATA tCONV N DATA tRX CONDITIONS: SMODE = V+, Bus = V+, HBE = DG or V+ 9 HI-7153 Typical Dynamic Performance Characteristics EFFECTIVE NUMBER OF BITS 10 65 SIGNAL-TO-NOISE RATIO 9 EFFECTIVE BITS 60 SNR (dB) 0 10 20 30 40 50 60 70 8 55 7 6 50 5 45 0 10 20 30 40 50 60 70 FREQUENCY (kHz) FREQUENCY (kHz) TOTAL HARMONIC DISTORTION -70 -65 -60 THD (dBc) -55 -50 -45 -40 NOISE (dB) -80 -75 -70 -65 -60 -55 -50 -45 0 10 20 30 40 50 60 70 -40 0 10 20 PEAK NOISE 30 40 50 60 70 FREQUENCY (kHz) FREQUENCY (kHz) SPURIOUS-FREE DYNAMIC RANGE 70 65 60 SFDR (dB) 55 50 45 40 0 10 20 30 40 50 60 70 FREQUENCY (kHz) 10 HI-7153 Typical Dynamic Performance Characteristics (Continued) FFT SPECTRUMS 0 -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) AMPLITUDE (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) NOTES: INPUT FREQUENCY: SAMPLING RATE: SNR: THD: PEAK NOISE: SPURIOUS FREE DYNAMIC RANGE: 3RD HARMONIC: 4931Hz 200kHz 59.40dB -67.26dB -75.98dB -68.36dB -77.19dB NOTES: INPUT FREQUENCY: SAMPLING RATE: SNR: THD: PEAK NOISE: SPURIOUS FREE DYNAMIC RANGE: 3RD HARMONIC: 14697Hz 200kHz 58.98dB -61.44dB -77.29dB -63.42dB -72.44dB 0 -10 -20 -30 AMPLITUDE (dB) -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) AMPLITUDE (dB) -40 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) NOTES: INPUT FREQUENCY: SAMPLING RATE: SNR: THD: PEAK NOISE: SPURIOUS FREE DYNAMIC RANGE: 3RD HARMONIC: 24462Hz 200kHz 58.36dB -55.59dB -76.65dB -57.72dB -64.53dB NOTES: INPUT FREQUENCY: SAMPLING RATE: SNR: THD: PEAK NOISE: SPURIOUS FREE DYNAMIC RANGE: 3RD HARMONIC: 4399Hz 200kHz 56.26dB -48.19dB -74.34dB -48.66dB -62.87dB 11 HI-7153 Pin Description DIP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL VREF AG AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 NC TEST A0 A1 A2 ALE DESCRIPTION Reference voltage input (+2.50V) Analog ground reference (0V) Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog input channel 5 Analog input channel 6 Analog input channel 7 No connect or tie to V+ only Test pin. Connect to DG for normal operation Mux address input. (LSB) Active high. Mux address input. (LSB) Active high. Mux address input. (MSB) Active high. Mux address enable. When high, the latch is transparent. Address data is latched on the falling edge. Write input. With CS low, starts conversion when pulsed low; continuous conversions when kept low. Chip select input. Active low. Read input. With CS low, enables output buffers when pulsed low; outputs updated at the end of conversion. Slow memory mode input. Active high. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OVR V+ GND V23 24 25 26 CLK DG EOC HOLD 22 HBE DIP PIN 21 SYMBOL BUS DESCRIPTION Bus select input. High = all outputs enabled together D0-D9, OVR Low = Outputs enabled by HBE Byte select (HBE/LBE) input for 8 bit bus. High = High byte select, D8 - D9, OVR Low = Low byte select, D0 - D7 Clock input. TTL compatible. Digital ground (0V) End-of-conversion status. Pulses high at the end-of-conversion. Start of conversion status. Pulses low at the start-of-conversion. Bit 0 (LSB) Bit 1 Bit 2 Output Bit 3 Data Bit 4 Bits Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 (MSB) Out of Range flag. Valid at end of conversion when output exceeds full scale. Positive supply voltage input (+5.0V) Ground return for comparators (0V) Negative supply voltage input (-5.0V) 17 WR 18 19 CS RD 20 SMODE Detailed Description The HI-7153 is an 8 channel high speed 10 bit A/D converter which achieves throughput rates of 200kHz by use of a Two Step Flash algorithm. A pipelined operation has been achieved through the use of switched capacitor techniques which allows the device to sample a new input voltage while a conversion is taking place. The 8 channel multiplexer can be randomly addressed. The HI-7153 requires a single reference input of +2.5V, which is internally inverted to 2.5V, thereby allowing an input range of -2.5V to +2.5V. The ten bits are two's complement coded. The analog and reference inputs are internally buffered by high speed CMOS buffers, which greatly simplifies the external analog drive requirements for the device. Analog to Digital Section The HI-7153 uses a conversion technique which is generally called a ``Two Step Flash'' algorithm. This algorithm enables very fast conversion rates without the penalty of high power dissipation or high cost. A detailed functional diagram is presented in Figure 1. The reference input to the HI-7153 is buffered by a high speed CMOS amplifier which is used to drive one end of the resistor string. Another high speed amplifier configured in the inverting unity gain mode inverts the reference voltage with respect to analog ground and forces it onto the other end of the resistor string. Both reference amplifiers are offset trimmed during manufacturing in order to increase the accuracy of the HI-7153 and to simplify its usage. 12 HI-7153 The input voltage is first converted into a 5 bit result (plus Out of Range information) by the flash converter. This flash converter consists of an array of 33 auto-zeroed comparators which perform a comparison between the input voltage and subdivisions of the reference voltage. These subdivisions of the reference voltage are formed by forcing the reference voltage and its negative on the two ends of a string of 32 resistors. The 5 bit result of the first flash conversion is latched into the upper five bits of double buffered latches. It is also converted back into an analog signal by choosing the ladder voltage which is closest to but less than the input voltage. The selected voltage (VTAP) is then subtracted from the input voltage. The residual is then amplified by a factor of 32 and referenced to the negative reference voltage (VSCA = 32(VIN - VTAP) + VREF-). This subtraction and amplification operation is performed by a Switched Capacitor amplifier (SCA). The output of the SCA amplifier is between the positive and negative reference voltages and can therefore be digitized by the original 5 bit flash converter (second flash conversion). The 5 bit result of the second flash conversion is latched into the lower five bits of double buffered latches. At the end of a conversion, 10 bits of data plus an Out of Range bit are latched into the second level of latches and can then be put on the digital output pins. The conversion takes place in three clock cycles and is illustrated in Figure 2. When the conversion begins, the track and hold goes into its hold mode for 1 clock cycle. During the first half clock cycle the comparator array is in its auto-zero mode and it samples the input voltage. During the second half clock cycle, the comparators make a comparison between the input voltage and the ladder voltages. At the beginning of the third half clock cycle, the first most significant 5 bit result becomes available. During the first clock cycle, the SCA was sampling the input voltage. After the first flash result becomes available and a ladder tap voltage has been selected the SCA amplifies the residue between the input and ladder tap voltages. During the next three half clock cycles, while the SCA output is settling to its required accuracy, the comparators go into their auto-zero mode and sample this voltage. During the sixth half clock cycle, the comparators perform another comparison whose 5 bit result becomes available on the next clock edge. Reference Input The reference input to the HI-7153 is buffered by a high speed CMOS amplifier. The reference input range is 2.2V to 2.6V. The reference input voltage should be applied following the application of V+ and V- supplies. 5 TO 32 DECODER (+VREF) AZ AZ 33 AZ AZ R 32 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 + REF (-) AMP (AG) R 2 AZ AZ AZ BUS CTRL BUS HBE LATCH AZ AZ AZ LATCH 32 TO 5 ENCODER AND OVR LOGIC AZ LATCHES AND OUTPUT BUFFER D9 OVR VREF AG + REF (+) AMP LATCH DATA OUTPUTS D0 1 LATCH (-VREF ) SCAZ SCAZ SCAZ C HOLD RD + (-VREF ) WR SWITCHED CAP. AMP CONTROL LOGIC CS SMODE CLK EOC SCAZ + TEST ALE MUX DECODER LATCHES TRACK BUFFER AMP HOLD CH (AG) + HOLD AMP SCAZ 32C POWER SUPPLY DISTRIBUTION A0 A1 A2 V+ V- GND DG FIGURE 1. DETAILED BLOCK DIAGRAM 13 HI-7153 Analog Multiplexer The multiplexer channel assignments are shown in Table 1 and can be randomly addressed. Address inputs A0 - A2 are binary coded and are TTL/CMOS compatible. During power up the circuit is initialized and multiplexer channel AIN0 is selected. The multiplexer address is transparent when ALE is high and CS is low. The address data is latched on the falling edge of the ALE signal. The multiplexer channel acquisition timing (Timing Diagrams, Slow Memory Mode) occurs approximately 500ns after the rising edge of HOLD. The multiplexer features a typical break-before-make switch action of 44ns. Track And Hold A Track and Hold amplifier has been fully integrated on the front end of the A/D converter. Because of the sampling nature of this A/D converter, the input is required to stay constant only during the first clock cycle. Therefore, the Track and Hold (T/H) amplifier ``holds'' the input voltage only during the first clock cycle and it acquires the input voltage for the next conversion during the remaining two clock cycles. The high input impedance of the T/H input amplifier simplifies analog interfacing. Input signals up to VREF can be directly connected to the A/D without buffering. The T/H amplifier typically settles to within 1/4 LSB in 1.5s. The A/D output code table is presented in Table 2. The timing signals for the Track and Hold amplifier are generated internally, and are also provided externally (HOLD) for synchronization purposes. All of the internal amplifiers are offset trimmed during manufacturing to give improved accuracy and to minimize the number of external components. If necessary, offset error can be adjusted by using digital post correction. TABLE 1. MULTIPLEXER CHANNEL SELECTION ADDRESS AND CONTROL INPUTS A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 CS 0 0 0 0 0 0 0 0 ALE 1 1 1 1 1 1 1 1 ANALOG CHANNEL SELECTED AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 N CONVERSION CLOCK 1 2 3 4 5 6 N+1 CONVERSION TRACK AND HOLD HOLD VIN (N) CONVERT UPPER 5 BITS TRACK VIN (N+1) HOLD VIN (N+1) CONVERT LOWER 5 BITS COMPARATOR AUTO-ZERO (AZ) SCA AUTO-ZERO (SCAZ) SAMPLE VIN (N) SAMPLE RESIDUAL SAMPLE VIN (N+1) SAMPLE VIN (N) AMPLIFY RESIDUAL SAMPLE VIN (N+1) INTERNAL DATA 10 BITS + OVR VIN (N) DATA FIGURE 2. INTERNAL ADC TIMING DIAGRAM TABLE 2. A/D OUTPUT CODE TABLE ANALOG INPUT* LSB = 2(VREF)/1024 +VREF +VREF - 1LSB +1LSB 0 -1LSB -VREF -VREF - 1LSB VREF = 2.500V 2.500 to V+ (+OVR) 2.49512 (+Full Scale) 0.00488 0.000 -0.00488 -2.500 (-Full Scale) 2.50488 to V- (-OVR) OVR 1 0 0 0 0 0 1 MSB 9 0 0 0 0 1 1 1 8 0 1 0 0 1 0 0 OUTPUT DATA (2'S COMPLEMENT) 7 0 1 0 0 1 0 0 6 0 1 0 0 1 0 0 5 0 1 0 0 1 0 0 4 0 1 0 0 1 0 0 3 0 1 0 0 1 0 0 2 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 LSB 0 0 1 1 0 1 0 0 * The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage. 14 HI-7153 Dynamic Performance Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance for one channel of the A/D system. A low distortion sine wave is applied to the input of the A/D converter. The input is sampled by the A/D and its output stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the converters dynamic performance such as SNR and THD. See typical performance characteristics. Signal-To-Noise Ratio The signal to noise ratio (SNR) is the measured rms signal to rms sum of noise at a specified input and sampling frequency. The noise is the rms sum of all except the fundamental and the first five harmonic signals. The SNR is dependent on the number of quantization levels used in the converter. The theoretical SNR for an N-bit converter with no differential or integral linearity error is: SNR = (6.02N + 1.76)dB. For an ideal 10 bit converter the SNR is 62dB. Differential and integral linearity errors will degrade SNR. Sinewave Signal Power SNR = 10 log ------------------------------------------------------Total Noise Power Microprocessor Interface The HI-7153 can be interfaced to microprocessors through the use of standard Write, Read, Chip Select, and HBE control pins. The digital outputs are two's complement coded, three-state gated, and byte organized for bus interface with 8 and 16 bit systems. The digital outputs (D0 - D9, OVR) may be accessed under control of BUS, byte enable input HBE, chip select, and read inputs for a simple parallel bus interface. The microprocessor can read the current data in the output latches in typically 60ns/byte (tRD). An over-range pin (OVR) together with the MSB (D9) pin set to either a logic 0 or 1 will indicate a positive or negative over-range condition respectively. All digital output buffers are capable of driving one TTL load. The multiplexer can be interfaced to either multiplexed or separate address and data bus systems. The HI-7153 can be interfaced to a microprocessor using one of three modes: slow memory, fast memory, or DMA mode. Slow Memory Mode In slow memory mode, the conversion will be initiated by the microprocessor by selecting the chip (CS) and pulsing WR low. This mode is selected by hardwiring the SMODE pin to V+. Note that the converter will change to the DMA interface mode if the WR to RD active timing is less than 100ns. The end-of-conversion (EOC) output signals an interrupt for the microprocessor to jump to a read subroutine at the end of conversion. When the 8 bit bus operation is selected, high and low byte data may be accessed in either order. An I/O truth table is presented in Table 3 for the slow memory mode of operation. Signal-To-Noise + Distortion Ratio SINAD is the measured rms signal to rms sum of noise plus harmonic power and is expressed by the following. Sinewave Signal Power SINAD = 10 log ------------------------------------------------------------------------------------------------------Noise + Harmonic Power (2nd thru 6th) Effective Number of Bits The effective number of bits (ENOB) is derived from the SINAD data; SINAD - 1.76 ENOB = ----------------------------------6.02 Total Harmonic Distortion The total harmonic distortion (THD) is the ratio of the RMS sum of the second through sixth harmonic components to the fundamental RMS signal for a specified input and sampling frequency. THD = 10 log Total Harmonic Power (2nd - 6th harmonics) -----------------------------------------------------------------------------------------------------------------Sinewave Signal Power Fast Memory Mode The fast memory mode of operation is selected by tying the SMODE and WR pins to DG. In this mode, the chip performs continuous conversions and only CS and RD are required to read the data. Whenever the SMODE pin is low, WR is independent of CS in starting a conversion cycle. During the first conversion cycle, HOLD follows WR going low. HOLD will be one clock period wide for subsequent conversion cycles. Data can be read a byte at a time or all 11 bits at once. When the 8 bit bus operation is selected, high and low byte data may be accessed in either order. EOC is continuously low in this mode of operation. The conversion data can be read after HOLD has gone low. An I/O truth table is presented in Table 4 for the fast memory mode of operation. Spurious-Free Dynamic Range The spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. It is usually determined by the largest harmonic. However, if the harmonics are buried in the noise floor it is the largest peak. Sinewave Signal Power SFDR = 10 log ---------------------------------------------------------------------------------Highest Spurious Signal Power DMA Mode This is a hardwired mode where the HI-7153 continuously converts. The user implements hardware to store the results in memory, bypassing the microprocessor. This mode is recognized by the chip when SMODE is connected to V+ and CS, RD, WR are connected to DG. When 8 bit bus operation is selected, high and low byte data may be accessed in either order. EOC is continuously low in this mode. The conversion data can be read approximately 300ns after HOLD has gone low. An I/O truth table is Clock The clock input is TTL compatible. The converter will function with clock inputs between 10kHz and 800kHz. 15 HI-7153 TABLE 3. SLOW MEMORY MODE I/O TRUTH TABLE (SMODE = V+) CS 0 0 1 0 0 0 X WR 0 X X X X X X RD X X X 0 0 0 1 BUS X X X 1 0 0 X HBE X X X X 0 1 X ALE X 1 X X X X X Initiates a conversion. Selects mux channel. Address data is latched on falling edge of ALE. Latch is transparent when ALE is high. Disables all chip commands. Enables D0 - D9 and OVR. Low byte enable: D0 - D7 High byte enable: D8 - D9, OVR Disables all outputs (high impedance). FUNCTION X = Don't Care TABLE 4. FAST MEMORY MODE I/O TRUTH TABLE (SMODE = DG) CS 0 0 1 0 0 0 X WR 0 X X X X X X RD X X X 0 0 0 1 BUS X X X 1 0 0 X HBE X X X X 0 1 X ALE X 1 X X X X X FUNCTION Continuous conversion, WR may be tied to DG. Selects mux channel. Address data is latched on falling edge of ALE. Latch is transparent when ALE is high. Disables all chip commands. Enables D0 - D9 and OVR. Low byte enable: D0 - D7 High byte enable: D8 - D9, OVR Disables all outputs (high impedance). X = Don't Care TABLE 5. DMA MODE I/O TRUTH TABLE (SMODE = V+, CS = WR = RD = DG) BUS X 1 0 0 HBE X X 0 1 ALE 1 X X X FUNCTION Selects mux channel. Address data is latched on falling edge of ALE. Latch is transparent when ALE is high. Enables D0 - D9 and OVR. Low byte enable: D0 - D7 High byte enable: D8 - D9, OVR X = Don't Care presented in Table 5 for the DMA mode of operation. fore, the system ground star connection should be located as close to this pin as possible. As in any analog system, good supply bypassing is necessary in order to achieve optimum system performance. The power supplies should be bypassed with at least a 20F tantalum and a 0.1F ceramic capacitor to GND. The reference input should be bypassed with a 0.1F ceramic capacitor to AG. The capacitor leads should be as short as possible. The pins on the HI-7153 are arranged such that the analog pins are well isolated from the digital pins. In spite of this arrangement, there is always some pin-to-pin coupling. Therefore the analog inputs to the device should not be driven from very high output impedance sources. PC board layout should screen the analog and reference inputs with guard rings on both sides of the PC board, connected to AG. Optimizing System Performance The HI-7153 has three ground pins (AG, DG, GND) for improved system accuracy. Proper grounding and bypassing is illustrated in Figure 3. The AG pin is a ground pin and is used internally as a reference ground. The reference input and analog input should be referenced to the analog ground (AG) pin. The digital inputs and outputs should be referenced to the digital ground (DG) pin. The GND pin is a return point for the supply current of the comparator array. The comparator array is designed such that this current is approximately constant at all times and does not vary with input voltage. By virtue of the switched capacitor nature of the comparators, it is necessary to hold GND firmly at zero volts at all times. There- 16 HI-7153 Applications Figure 4 illustrates an application where the HI-7153 is used to form a multi-channel data acquisition system. Either slow memory or fast memory modes of operation can be selected. Fast memory mode should be selected for maximum throughput. The output data is configured for 16 bit bus operation in these applications. By tying BUS to DG and connecting the HBE input to the system address decoder, the output data can be configured for 8 bit bus systems. -5V P.S. 0.1F 0.1F 20F 20F + -5V P.S. + +2.5 REF 0.1F 1 VREF 2 AG 3 AIN0 4 AIN1 V- 40 GND 39 V+ 38 OVR 37 D9 36 D8 35 D7 34 D6 33 D5 32 D4 31 D3 30 D2 29 D1 28 D0 27 HOLD 26 EOC 25 DG 24 CLK 23 HBE 22 BUS 21 ANALOG INPUT 5 AIN2 6 AIN3 7 AIN4 8 AIN5 9 AIN6 10 AIN7 11 NC 12 TEST 13 A0 14 A1 15 A2 16 ALE 17 WR 18 CS 19 RD 20 SMODE FIGURE 3. GROUND AND POWER SUPPLY DECOUPLING ADDRESS BUS ADDRESS DECODER A0 - A2 VREF SIGNAL GND +5V AG CS WR MICROPROCESSOR HI-7153 V+ RD ALE EOC CLK D0 - D9, OVR 8 BIT DATA BUS 600kHz -5V VDG GND TEST FIGURE 4. MULTI-CHANNEL DATA ACQUISITION SYSTEM 17 |
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